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Renesas Electronics /R7FA6M1AD /GPT_ODC /GTDLYCR

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Interpret as GTDLYCR

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DLLEN 0 (0)DLYRST

DLYRST=0, DLLEN=0

Description

PWM Output Delay Control Register

Fields

DLLEN

DLL Operation Enable

0 (0): Disable DLL operation

1 (1): Enable DLL operation
DLYRST

PWM Delay Generation Circuit Reset

0 (0): Normal operation

1 (1): Reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data